Venue: TRAVANCORE COURT, Warriam Road, Ernakulam, Cochin - 16. Ph.No.: 0484-2351120, 0484-4031120, 0484-4021120,
Infotech Hyderabad - Mobile: +91 92463 72722,
Infotech Bengaluru - Mobile: +91 90088 55911
Note: To book for specific time slots, please ask candidates to call or SMS to the Infotech Mobile nos.
Date : 2nd & 3rd June 2012 (Saturday & Sunday).
Walk-in Time: 10.00 AM to 2:00 PM.
A snapshot of our Hitech practice:
Ø One of the largest ASIC design and Embedded SW services teams
Ø 14-year track record of first pass silicon success across 300+ ASIC tapeouts
Ø In-depth expertise on various EDA tool flows that positions us way ahead of the competition
Ø A niche player in platform development based on Android, Linux, WinCE and other embedded OS
Ø Preferred Embedded SW solution provider for top 3 OEMs and topmost chipset vendors
Ø Globally distributed design centers - San Jose, California (US), Hyderabad, Visakhapatnam and Bengaluru
EMBEDDED SOFTWARE REQUIREMENTS
Job Location: Bengaluru
Qualification: BE/B.Tech. or ME/M.Tech. in ECE/EEE/CSE
Experience: 3 - 7 years
VC++, MFC, Win32 (Job Code: MFC)
· Experience using VC++ with MFC and Win32, sound knowledge of OOPs concepts, multi-threading
· Understanding of STL, Windows Sockets and .Net Technologies
LTE Physical Firmware/DSP (Job Code: LPF/DSP)
· Signal processing background with good understanding of OFDM, MIMO
· Strong C, Embedded and real time programming, C/Assembly on DSPs/RISCs
· Experience in Lab tools/Analyzers/Emulators
LTE MAC Firmware (Job Code: LMacF)
· Experience in L2 (MAC) firmware, hands-on working experience in C/assembly
· Upper MAC, lower MAC, LTE experience preferred
· Linux internals such as device drivers, networking interfaces, QoS and the TCP/IP stack
· Experience in Lab tools/Analyzers/Emulators/embedded systems/microcontroller
· Signal processing understanding, concept of OFDM, MIMO
Android Multimedia frameworks (Job Code: Android MF)
· Strong knowledge of C/C++ and multimedia fundamentals
· Hands-on experience in Linux/Android multimedia framework Opencore/Openmax/Stagefright on HW platforms/SOCs
· Expertise in any of the following:
- Pre/Post Processing/Algorithms: Video surveillance, Video Analytics, IP camera segment
- Microsoft DirectShow or SGX/OpenGL/ES, familiarity with multimedia encoders and decoders would be an added advantage
BSP–Linux Device Driver (Job Code: BSP Linux)
· Good understanding of processor (ARM, MIPS, x86) and overall system architecture
· Well versed with OS internals and mobile platform SW (Linux/WinCE/Android)
· Firmware and device driver development for mobile and set top box based platforms (PM, Connectivity/MM devices/Memory Devices/HID/Bus devices ± USB/PCI etc)
· Developing Board Support Package (BSP), boot loaders, OS porting and bring up on SDPs
Wi-Fi (Job Code: Wi-Fi)
· Proficiency in C/C++ and assembly programming skills
· Expertise on any mobile OS-Linux/Android/WinCE/WinMobile, good knowledge of connectivity buses - SDIO/SPI/PCI/USB
· Strong working and testing knowledge with IEEE802.11 a/b/g/n, Wi-Fi Protocol
· Experience with Wi-Fi Display and Wi-Fi Direct related technologies
· Exposure to Wi-Fi forum certification, WiFi lab setup would be an added advantage
ASIC & FPGA REQUIREMENTS
Positions are available for the role of Project Engineer, Sr.Project Engineer, Tech Lead, Project Lead, Project Manager and Program Manager in the following domains
ASIC/SoC Verification (Job Code: ASIC-Ver)
Experience: 3 - 15 years
One or more of the following skills
· Expertise in HVL like Secman or SystemVerilog OVM/VMM/UVM/eRM
· Exposure to SoC verification around ARM, MIPS, Tensilica and peripherals using C/ASM
· Expertise in analog and mixed signal verification
Job Location: Hyderabad, Bengaluru, Visakhapatnam & Nodia
Logic Design (Job Code: ASIC/FPGA-LD)
Experience: 3 - 15 years
Microarchitecture, Logic Design, RTL Coding, Logic Synthesis, expertise on ARM and Cortex processors and designing subsystems around them
Job Location: Hyderabad, Bengaluru & Noida
ASIC Physical Design Engineers/Leads (Job Code: ASIC-PD)
Experience: 2 - 8 years
Experience in partitioning, IO Ring Preparation, Floor Planning, PG Planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop Analysis, Physical Verification, Signal Integrity, Low Power Design
Job Location: Hyderabad, Bengaluru, Visakhapatnam & Noida
ASIC Physical Design Managers (Job Code: ASIC-PDM)
Experience: 8 - 14 years
· Should be able to manage a team of 10+ physical design engineers with expertise on Partitioning, IO ring preparation, Floorplanning, PG planning, Place and Route, Clock Tree Synthesis, Timing
Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power Design
· Experience should include managing multi-million gate hierarchical designs using deep submicron process technologies
Job Location: Hyderabad, Bengaluru & Visakhapatnam
ASIC Implementation (Job Code: ASIC-IMP)
Experience: 4 - 10 years
· Experience in Logic Synthesis, Low Power Synthesis, Timing Constraints, Timing Closure, Static Timing Analysis, Cross Talk Analysis & Repair, Formal Verification
Job Location: Hyderabad, Bengaluru & Visakhapatnam
ASIC Standard Cell/Memory/IO/Analog (Job Code: ASIC-Standard Cell/Memory/IO/Analog)
Experience: 2 - 5 years
· Hands-on experience in layout design of Standard Cell/Memory/IO/Analog
Job Location: Hyderabad, Bengaluru & Noida
ASIC DFT (Job Code: ASIC-DFT)
Experience: 2 - 8 years
· Expertise in scan, test compression, ATPG, LBIST, MBIST,JTAG, ATE equipment, test mode timing, simulation, silicon debug
Job Location: Bengaluru, Hyderabad & Visakhapatnam
FPGA Positions:
FPGA Design and Verification(Job Code: FPGA)
Experience: 2 - 15 years (Tech lead/Senior Engineer/Junior Engineer)
· Experience in design, verification & validation for FPGA based systems
· Expertise in verification using system verilog (OVM/UVM), Verilog or VHDL
· FPGA based design implementation on Actel, ALTERA, XILINX
· Experience in Aerospace or Rail Domain would be an added advantage
Job Location: Hyderabad & Bengaluru
Qualification for all the above positions: BE/B.Tech or ME/M.Tech/MS in respective streams for Hitech ASIC & FPGA
What is the Enhanced Referral Program?
Associate will be rewarded for each referral leading to the successful on-boarding based on the management cadre mentioned below:
· Team Member (Level 3 & 4) - INR 35,000
· Junior Management (Level 5, 6 & 7) – INR 50,000
· Middle Management (Level 8, 9 & 10) - INR 75,000
What do you need to keep in mind?
· Referrals sent to the designated email only will be considered
· Referrals where new joinees leave within 3 months will not be eligible for payouts
· The bonus amount can be claimed after 3 months from the date of joining of the referred candidate
· The referral will be valid for a period of 1 month from the date of referral
What you need to do?
1. Forward suitable profiles to the designated e-mail ID mentioning 'job code' and 'years of experience' in the subject line.
2. Any referral made between the date of this circular and 30th June 2012 for the Embedded Software , ASIC & FPGA skills resulting in recruitment (offer made) on or before 16th July 2012 will qualify you for the enhanced reward.
Candidates who are unable to attend the drive can forward their resumes mentioning "Job Code & Years of Experience" in the Subject line to: Hitech -ASIC & FPGA requirements :- Praveen.Vemula@infotech-enterprises.com & for Hitech – Embedded Software requirements Srinivas.Dodla@infotech-enterprises.com
Download Java / .NET / Testing etc.. eBooks @ http://rfc-ebooks.blogspot.com
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